The present invention relates to a semiconductor device and a method of fabricating the same.
The development of semiconductor integrated circuits largely depends upon an excellent property, i.e., the scaling law (the standard of micropatterning) of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a constituent element. That is, in a semiconductor integrated circuit, the number of MOSFETS integrated in a limited chip area can be increased by reducing the dimensions of these MOSFETs on the basis of this scaling law.
If micropatterning progresses in a conventional planar type MOSFET, however, the standby power (the power consumption in a standby state) abruptly increases, and this limits the progress of micropatterning.
In this planar type MOSFET, when dimensions are reduced on the basis of the scaling law, the impurity concentration in a channel region must be increased accordingly. If the impurity concentration in the channel region of the planar type MOSFET increases, however, the capacitive coupling between the channel region and a semiconductor substrate increases. This reduces the inversion charge amount, and lowers the drivability.
In the planar type MOSFET, therefore, a gate threshold voltage must be lowered to maintain given drivability. However, if this gate threshold voltage is lowered, a cutoff current (OFF current) exponentially increases.
Also, in the planar type MOSFET, if the impurity concentration in the channel region increases, a junction leakage current or surface leakage current increases. This further increases the standby power.
For example, when the gate length is 50 [nm], the standby power may exceed the active power (the power consumption during operation). In this case, even if micropatterning is performed to avoid the problem of heat generation, it is impossible to integrate a large number of planar type MOSFETs on a chip, so the integration degree cannot be increased.
To suppress this increase in standby power, a MOSFET (to be referred to as a FinFET hereinafter) having a vertical double gate structure is developed as a new transistor structure which replaces the planar type MOSFET.
In this FinFET, a semiconductor layer having the shape of a fin, i.e., a projecting shape is formed on a semiconductor substrate, and an inverted U-shaped gate electrode is formed on two side surfaces and the upper surface of the semiconductor layer via an insulating film so as to cross the semiconductor layer. Also, in the FinFET, a source region and drain region are formed on a pair of opposing side surfaces, on which the gate electrode is not formed, of the four side surfaces of the semiconductor layer.
In this FinFET, the gate electrode is formed on the two side surfaces of the semiconductor layer. Therefore, if the width of this semiconductor layer (i.e., the spacing between the legs of the gate electrode) is sufficiently small, the charge amount in a channel region formed in the semiconductor layer strongly depends upon the gate electric field formed by the gate electrode. Therefore, the FinFET does not easily suffer the influence of the capacitive coupling between the channel region and semiconductor substrate. As a consequence, the inversion charge amount does not depend upon the impurity concentration in the channel region any longer.
Also, in the FinFET, the charge amount in the channel region strongly depends on the gate electric field. Therefore, the FinFET does not easily suffer the influence of the capacitive coupling between the channel region and drain region. This suppresses the short channel effect. In the FinFET, therefore, the increase in standby power caused by micropatterning can be minimized.
To actually suppress the short channel effect in the FinFET, the width of the semiconductor layer must be decreased to at least half the gate length (the spacing between the source region and drain region). Since, however, such a FinFET is difficult to fabricate, a method of suppressing the short channel effect more efficiently is being sought.
Similar to a planar type MOSFET using an SOI (Silicon On Insulator) substrate, a FinFET using an SOI substrate has a majority carrier storage effect (body floating effect) and self-heating effect. This fluctuates the threshold voltage or lowers the drivability (described in, e.g., the following patent reference).
Patent reference: Japanese Patent Laid-Open No. 6-302819